1. Field of the Invention
The present invention relates to a method of forming an isolation trench. More particularly, the present invention relates to a method of doping sidewalls of an isolation trench.
2. Description of the Related Art
The isolation region of a semiconductor device is a form of partition between neighboring field effect transistor for preventing the cross diffusion of currents. Putting up an isolation trench is an effective method of isolating devices. To form an isolation trench, a pad oxide layer and a polishing stop layer are formed over a substrate. Thereafter, an anisotropic dry etching is carried out to form a trench in the semiconductor substrate. Finally, an insulation material is deposited to fill the trench serving as a device isolation structure.
Because the device that crosses over the isolation region and the corner of the active area has a relatively large electric field near the active area corner, sub-threshold leakage current has become an increasingly important problem for device operation. With the miniaturization of transistor devices and hence the reduction of channel width, the sub-threshold leakage current will be increasingly dominant resulting in the so-called narrow channel width effect. To reduce the severity of narrow channel width effect, U.S. Pat. No. 5,960,276 disclosed a method of doping sidewalls of an isolation trench. FIG. 1 is a schematic cross-sectional view showing a conventional method of doping the sidewalls of an isolation trench. First, a pad oxide layer 101 and a polishing stop layer 102 is formed over a substrate 100. Thereafter, an anisotropic dry etching is carried out to form a trench 104 in the substrate 100. A photolithographic process is carried out to form a mask layer 109. The mask layer blocks the PMOS region but exposes the NMOS region. Finally, a sidewall doping operation 106 is carried out to from a doped region 110 in the substrate 100 along the sidewalls of the trench 104.
After the sidewall doping operation 106, the doped region 110 not only spreads over the top section of the trench sidewall but also the lower and bottom section of the trench sidewall. The doped region 110 on the sidewall of the trench may overlap with the doped source/drain region of a subsequently formed transistor and increase their junction gradient. Hence, the electric field in the junction area will increase leading to a possible increase in junction leakage.